1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device including a latency counter that delays an internal command signal.
2. Description of Related Art
A synchronous memory device, represented by a synchronous DRAM (Dynamic Random Access Memory), has been widely used for a main memory of a personal computer and the like. The synchronous memory device inputs or outputs data in synchronization with a clock signal supplied from a controller. Therefore, the use of a higher-speed clock leads to an increase in data transfer rate.
However, even in the synchronous DRAM, a DRAM core still operates in an analog mode, requiring a sense operation to amplify extremely weak electric charges. As a result, it is not possible to reduce the time required to output the first data after a read command is issued. Therefore, after a predetermined delay time has passed since the issuing of the read command, the first data are output in synchronization with an external clock signal.
The delay time in the read operation is usually referred to as “CAS latency,” and is set to the integral multiple of a clock cycle. For example, when the CAS latency is five (CL=5), the first data are output in synchronization with an external clock signal that appears five cycles after a read command is captured in synchronization with an external clock signal. That is, five clock cycles later, the first data are output.
Such a delay is necessary even for a write operation. In the write operation, after a predetermined delay time has passed since the issuing of a write command, data need to be input sequentially in synchronization with external clock signal. The delay time in the write operation is usually referred to as “CAS write latency,” and is set to the integral multiple of a clock cycle. For example, when the CAS write latency is five (CWL=5), the first data need to be input in synchronization with an external clock signal that appears five clock cycles after the write command is captured in synchronization with an external clock signal.
Moreover, what is employed by a DDR2 (Double Data Rate 2) or later model SDRAM is a Posted CAS method, which enables a controller to issue a read or write command to asynchronous memory device at an earlier timing than an original issuing timing. How far the command issuing timing is moved forward, i.e. the difference between the original timing at which the read or write command should be issued and the actual, earlier timing at which the read or write command is issued, is referred to as additive latency (AL). Therefore, in the read operation for example, the period required to start outputting read data after the read command is issued is defined as AL+CL.
When the Posted CAS method is employed, a semiconductor device (synchronous memory device) does not start a column-system control circuit immediately after a memory controller issues a read or write command. The semiconductor device needs to wait to start the column-system control circuit until the additive latency has passed. What is used for the above purpose is a FIFO circuit that delays a read or write command, which is supplied from the outside, in the semiconductor device. Such a FIFO circuit is generally referred to as a “latency counter.” The most commonly used latency counter is a shift register.
An inventor of the present invention has previously proposed a new latency counter (Japanese Patent Application Laid-Open No. 2010-3397). The latency counter disclosed in Japanese Patent Application Laid-Open No. 2010-3397 uses a circuitry section, which selects whether a latency is an odd or even number, and a circuitry section, which gives a delay to an internal command signal at intervals of two clock cycles; the circuitry sections are connected in parallel to make circuits smaller in size and reduce power consumption. In recent years, the pace at which the wiring pitch is reduced has not kept up with the pace at which transistors become smaller in size. As a result, a new issue has arisen that as a circuit is made smaller in size, sufficient numbers of lines of the circuit cannot be formed on the top of the circuit.